1. Field of the Invention
The present invention relates to a memory component and, in particular, to a memory component having a novel arrangement of the bit lines, which arrangement reduces the influence of capacitive couplings between adjacent bit lines.
2. Description of the Related Art
In dynamic random access memory (DRAM) components and other memory modules, the memory cells are arranged at crossover points between bit lines and word lines. Activating a word line or applying an appropriate signal to the word line connects each memory cell that is associated with the word line to the bit line on which it is arranged.
Reference is made below, by way of example, to a dynamic memory component. Two bit lines are respectively typically connected to a sense amplifier. The sense amplifier operates in a differential manner and compares the potentials of the two bit lines which are connected to it. Activating a word line connects one of the two bit lines to a memory cell (active bit line). The other bit line which is connected to the same sense amplifier is used as a reference bit line which does not have a memory cell connected to it at present.
Before a word line is activated, all of the bit lines are brought, in a precharge operation, to a center potential Vbleq which is between a high potential Vblh and a low potential Vbll.
After the word line has been activated, connecting the active bit line to that memory cell which is associated with the crossover point between the active bit line and the word line gives rise to a small potential difference caused by the charge stored in the memory cell. This small potential difference is amplified by the sense amplifier. In this case, one of the two bit lines assumes the high potential Vblh and the other assumes the low potential Vbll, depending on the charge or information stored in the memory cell. As a result, the charge stored in the memory cell is simultaneously refreshed.
If the memory cell is disconnected from the active bit line again as a result of the word line being deactivated, the two bit lines are precharged or brought to the center potential Vbleq again. In this case, the two bit lines which are connected to the sense amplifier are shorted together by means of a switch. If the two bit lines have approximately the same electrostatic capacitance, a potential is approximately established in the middle between the high potential Vblh and the low potential Vbll, said potential corresponding to the center potential Vbleq. In order to compensate for small asymmetries, the two bit lines are also connected, simultaneously or subsequently, to a Vbleq system via switches which are provided for this purpose, said system providing the center potential Vbleq.
A frequent defect which, on statistical average, occurs once or a number of times on each chip is a short circuit between a word line and a bit line at the crossover point between them. In the case of DRAMs, this short circuit occurs particularly frequently at the selection transistor of a memory cell. The word line involved is replaced with a redundant word line. Although the bit line involved is likewise replaced with a redundant bit line, the switches for connecting the bit lines to the Vbleq system during precharging are conventionally not driven individually. When precharging the bit lines, a bit line which has been shorted to a word line is therefore also connected to the Vbleq system. Since the word line has a potential that differs from the center potential Vbleq, the Vbleq system is subjected to loading on account of the bit line being shorted to the word line and can no longer provide precisely the center potential Vbleq.
In order to minimize the load on the Vbleq system and the induced discrepancy between the potential of the latter and the center potential Vbleq, the switches for connecting the bit lines to the Vbleq system are designed to have a high impedance. The resultant large time constant for matching the potential of a bit line to the center potential Vbleq provided by means of the Vbleq system does not constitute a disadvantage since the bit lines, as described above, are primarily approximated to the center potential Vbleq by shorting them in pairs, and only small asymmetries need to be compensated for using the high-impedance switches.
However, there are various situations in which, as a result of capacitive coupling between adjacent bit lines, there is a relatively large discrepancy between the potential of a bit line and the center potential Vbleq, which discrepancy needs to be compensated for by the Vbleq system using the high-impedance switch. Adjacent bit lines always influence one another via their capacitive coupling. It is assumed that a first bit line of a first sense amplifier is directly adjacent to a second bit line of a second sense amplifier, and a third bit line of the first sense amplifier is directly adjacent to a fourth bit line of a third sense amplifier. If the second bit line and the fourth bit line have the same potential, their influences on the first and third bit lines do not cancel one another out. After the first and third bit lines have been shorted, the latter therefore have an average potential that differs from the center potential Vbleq. The Vbleq system must compensate for this discrepancy using the high-impedance switches.
The situation described below occurs, in particular, in the case of a memory element whose bit lines are arranged in accordance with the open bit line concept. In accordance with the open bit line concept, the sense amplifiers are arranged in a plurality of parallel rows. The two bit lines which are connected to a sense amplifier extend from the latter in two opposite directions perpendicular to the rows. In the interspace between two rows of sense amplifiers, the bit lines which are connected to sense amplifiers in the two rows intermesh like two combs. To put it another way, the bit lines in an interspace are always alternately connected to a sense amplifier in one row and a sense amplifier in the other row.
Activating a word line between a first row and a second row of sense amplifiers causes all of the bit lines in the interspace between the first and second rows to become active bit lines. All of the bit lines (which are connected to sense amplifiers in the first row) in an interspace between the first row and an adjacent third row and all of the bit lines (which are connected to sense amplifiers in the second row) between the second row and an adjacent fourth row become reference bit lines. The potentials of the bit lines, which are arranged between the reference bit lines, of the sense amplifiers in the third and fourth rows are influenced by capacitive coupling to said reference bit lines. The Vbleq system must compensate for the resultant discrepancies between said potentials and the center potential Vbleq using the high-impedance switches.